A byte-addressable main memory of size 64MB with blocks of size 64B. The cache memory has 256 blocks ( the block is also of size 64B) in addition to the space for tag and validity bit.
For each of the following cache organization, determine the number of bits of Byte Offset, Tag, and index (block number in cache for direct Mapped organization) and the set ( number in the 2-way set associative), and fully associative.
For each one of the three organizations, determine whether each of the following memory addresses is a hit or a miss.
2, 16, 210 +7, 212 + 28 , 212 + 7, 63, 210 +12, 210 , 215 +1, 4
Assume the cache blocks initially are not used.
Create a table for each organizations and show the cache content after each above reference and indicate whether the reference is a hit or a miss

26 bits of address space, divided into a 2 bit "byte offset," a 2 bit "word offset," a tag, and an 8 bit cache index, are needed for 64 MB (256 entries in the cache).

How many bits are required to represent a 64 MB address space?

26 bits of address space, divided into a 2 bit "byte offset," a 2 bit "word offset," a tag, and an 8 bit cache index, are needed for 64 MB (256 entries in the cache).

As a result, the tag has 14 bits (26 – 2 – 2 – 8 = 14). The byte offset and word offset, respectively, use bits 0, 1, and 2, 3.As a result, the cache is made up of 256 groups of two lines each.

The set number must therefore be identified using 8 bits.In theory, 16 EiB (16 10246 = 264 = 18,446,744,073,709,551,616 bytes, or roughly 18.4 exabytes) of memory can be addressed by a 64-bit processor.A full 64-bit virtual or physical address space is supported by some instruction sets, but not by all processors that implement such instruction sets.

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